Field of the Technology
The technology disclosed relates to memory devices based on phase change memory materials, like chalcogenides, and on other programmable resistance materials, and methods for operating such devices.
Description of Related Art
In some programmable resistance memory array configurations, each memory cell includes a diode or a transistor in series with a programmable resistance memory element. The diode or transistor acts as an access device, so that memory cells can be selected for program or read operations, while current flow in unselected memory cells is blocked.
One type of programmable resistance memory element includes phase change material that exhibit a large resistivity contrast between crystalline (low resistivity) and amorphous (high resistivity) phases. Phase change materials may include chalcogenides, and other alloys of materials such as germanium (Ge), antimony (Sb), tellurium (Te), gallium (Ga), indium (In), silver (Ag), selenium (Se), thallium (Ti), bismuth (Bi), tin (Sn), copper (Cu), palladium (Pd), lead (Pb), sulfur (S), and gold (Au). In normal operation of a phase change memory element, an electrical current pulse passed through the phase change memory cell can set or reset the resistivity phase of the phase change memory element. To reset the memory element into the amorphous phase, an electrical current pulse with a large magnitude for a short time period can be used. To set the memory element into the crystalline phase, an electrical current pulse with an intermediate magnitude and a longer time period can be used. To read the state of the memory element, a small voltage is applied to the selected cell and the resulting electrical current is sensed. The sensed current may have at least two current levels, one very low for a high resistance state, and another higher for a low resistance state. Accordingly, an electrical current is used when an operation is needed to set, reset or read the resistivity state of a selected memory cell.
Memory cells in phase change memory devices experience a statistical process variation during program operations, resulting in normal distributions for respective resistance ranges that represent logic levels. A very small portion of memory cells in a phase change memory array can fall out of the normal distributions, and are referred to as tail bits. Tail bits can affect the reliability of phase change memory devices, especially in MLC (multiple level cell) phase change memory devices, where the resistance ranges are closer to each other than in SLC (single-level cell) phase change memory devices.
A set-verify-set operation is a way to fix the tail bits during set operations to set memory elements into the crystalline phase. In a set-verify-set operation, a set pulse is applied to a memory element and subsequently a verify pulse is applied to the memory element to verify whether the memory element is set to within an expected range of resistance. If not, another set pulse is applied to the memory element, and the set-verify-set operation is repeated until the memory element is set to within the expected range of resistance. However, the set-verify-set operation can impact the program performance of the memory device, because to switch between a set operation and a verify operation for a memory cell, the bias arrangements for the bit line and word line coupled to the memory cell must be changed.
It is desirable to provide technology which can improve the program performance of a phase change memory device.